FPGA 18 工程模块 uart_Rx串口接收模块设计

桃扇骨 2022-09-01 14:55 256阅读 0赞

![\[外链图片转存失败,源站可能有防盗链机制,建议将图片保存下来直接上传(img-tJ10RlUP-1627476172046)(/img/blog\_img/fpga/test.png)\]][img-tJ10RlUP-1627476172046_img_blog_img_fpga_test.png]

# FPGA 18 工程模块 uart\_Rx串口接收模块设计 #

![\[外链图片转存失败,源站可能有防盗链机制,建议将图片保存下来直接上传(img-nHBDRQ4S-1627476172049)(img/blog\_img/fpga/image-20210728204052669.png)\]][img-nHBDRQ4S-1627476172049_img_blog_img_fpga_image-20210728204052669.png]

模块名称： uart\_byte\_rx IP Core

主要功能 ：串口数据接收模块

实现（设计）流程：在波特率设置端口使用查找表实现，波特率时钟计数器的设置，在波特率时钟计数器端口，根据数值产生对应的时钟，同时，读取输入的 Rs232\_Rx 信号进行采样处理，考虑在工业的应用情况，我们对信号实现16倍信号速率采样，进而判断每个bit的 ’0‘和’1‘ 信号，最后，在内部实现串并转换过程，得到最后的串口数据输出 data\_byte\[7:0\].

实验目的 ：

1、UART 通信协议在工业场景的实现

2、ISSP 调试的使用

3、信号采样的概念，已经数据的解析（判决分析）.

在普通环境或者实验室环境中，对于其中的每一位进行采样,一般情况下每一位数据的中间点是最稳定的,因此一般应用中，采集中间时刻时的数据即可，如下图所示:

![\[外链图片转存失败,源站可能有防盗链机制,建议将图片保存下来直接上传(img-4soaCja2-1627476172050)(E:/Blog\_Template/source/\_posts/img/blog\_img/fpga/image-20210312122837649.png)\]][img-4soaCja2-1627476172050_E_Blog_Template_source_posts_img_blog_img_fpga_image-20210312122837649.png]

但是在工业应用中，往往有非常强的电磁干扰，只采样一次就作为该数据的电平判定，是不保险的，有可能恰好采集到被干扰的信号而导致结果出错，因此需要使用【多次采样求概率】的方式进行。

以下为改进型的单bit数据接收方式示意图:

![\[外链图片转存失败,源站可能有防盗链机制,建议将图片保存下来直接上传(img-9VThmNt8-1627476172052)(E:/Blog\_Template/source/\_posts/img/blog\_img/fpga/image-20210312123542400.png)\]][img-9VThmNt8-1627476172052_E_Blog_Template_source_posts_img_blog_img_fpga_image-20210312123542400.png]

我们采用16倍采样，每个bit采样16次，在图中可以看到红色区域（左边5次采样，右边5次采样）中，我们认为是一个会被干扰的数据，中间绿色的部分我们认为是稳定的信号（一共6次），只要这6次采集的数据的概率做一个比较，然后判决有效的信号即可。

设计文件：

module uart_byte_rx(
    	Clk,
    	Rst_n,
    	baud_set,
    	Rs232_Rx,
    	
    	data_byte,
    	Rx_Done
    );
    
    	input Clk;
    	input Rst_n;
    	input [2:0]baud_set;
    	input Rs232_Rx;
    	
    	output reg [7:0]data_byte;
    	output reg Rx_Done;
    	
    	reg s0_Rs232_Rx,s1_Rs232_Rx;//同步寄存器
    	
    	reg tmp0_Rs232_Rx,tmp1_Rs232_Rx;//数据寄存器
    	
    	reg [15:0]bps_DR;//分频计数器计数最大值
    	reg [15:0]div_cnt;//分频计数器
    	reg bps_clk;//
    	reg [7:0]bps_cnt;
    	
    	reg uart_state;
    	
    	reg [2:0] r_data_byte [7:0];
    	reg [7:0] tmp_data_byte;
    	reg [2:0] START_BIT,STOP_BIT;
    	
    	wire nedege;
    	
    	//同步寄存器，消除亚稳态
    	always@(posedge Clk or negedge Rst_n)
    	if(!Rst_n)begin
    		s0_Rs232_Rx <= 1'b0;
    		s1_Rs232_Rx <= 1'b0;	
    	end
    	else begin
    		s0_Rs232_Rx <= Rs232_Rx;
    		s1_Rs232_Rx <= s0_Rs232_Rx;	
    	end
    	
    	//数据寄存器
    	always@(posedge Clk or negedge Rst_n)
    	if(!Rst_n)begin
    		tmp0_Rs232_Rx <= 1'b0;
    		tmp1_Rs232_Rx <= 1'b0;	
    	end
    	else begin
    		tmp0_Rs232_Rx <= s1_Rs232_Rx;
    		tmp1_Rs232_Rx <= tmp0_Rs232_Rx;	
    	end
    	
    	assign nedege = !tmp0_Rs232_Rx & tmp1_Rs232_Rx;
    	
    	//1、波特率设置计数器模块
    	always@(posedge Clk or negedge Rst_n)
    	if(!Rst_n)
    		bps_DR <= 16'd324;
    	else begin
    		case(baud_set)
    			0:bps_DR <= 16'd324;  	// 9600bps
    			1:bps_DR <= 16'd162;	// 19200bps
    			2:bps_DR <= 16'd80;		// 38400bps
    			3:bps_DR <= 16'd53;		// 57600bps
    			4:bps_DR <= 16'd26;		// 115200bps
    			default:bps_DR <= 16'd324;			
    		endcase
    	end
    	
    	//2、计数器计数模块
    	always@(posedge Clk or negedge Rst_n)
    	if(!Rst_n)
    		div_cnt <= 16'd0;
    	else if(uart_state)begin
    		if(div_cnt == bps_DR)
    			div_cnt <= 16'd0;
    		else
    			div_cnt <= div_cnt + 1'b1;
    	end
    	else
    		div_cnt <= 16'd0;
    		
    	//3、计数器串口时钟  bps_clk 生成模块
    	always@(posedge Clk or negedge Rst_n)
    	if(!Rst_n)
    		bps_clk <= 1'b0;
    	else if(div_cnt == 16'd1)
    		bps_clk <= 1'b1;
    	else
    		bps_clk <= 1'b0;
    	
    	//4、采样时钟 bps counter 统计模块
    	always@(posedge Clk or negedge Rst_n)
    	if(!Rst_n)	
    		bps_cnt <= 8'd0;
    	else if(bps_cnt == 8'd159 | (bps_cnt == 8'd12 && (START_BIT > 2)))
    		bps_cnt <= 8'd0;
    	else if(bps_clk)
    		bps_cnt <= bps_cnt + 1'b1;
    	else
    		bps_cnt <= bps_cnt;
    	
    	//5、采样完成信号Rx_Don处理模块
    	always@(posedge Clk or negedge Rst_n)
    	if(!Rst_n)
    		Rx_Done <= 1'b0;
        else if(bps_cnt == 8'd159)  //接收完成后，让 Rx_Done ==1'b1
    		Rx_Done <= 1'b1;
    	else
    		Rx_Done <= 1'b0;
    
    //  会导致信号的延时一拍输出
    //	always@(posedge Clk or negedge Rst_n)
    //	if(!Rst_n)
    //		data_byte <= 8'd0;
    //	else if(bps_cnt == 8'd159)
    //		data_byte <= tmp_data_byte;
    //	else
    //		data_byte <= data_byte;
    		
    		
    
    	//6、采样数据处理（相加）模块	
    	always@(posedge Clk or negedge Rst_n)
    	if(!Rst_n)begin
    		START_BIT = 3'd0;
    		r_data_byte[0] <= 3'd0;
    		r_data_byte[1] <= 3'd0;
    		r_data_byte[2] <= 3'd0;
    		r_data_byte[3] <= 3'd0;
    		r_data_byte[4] <= 3'd0;
    		r_data_byte[5] <= 3'd0;
    		r_data_byte[6] <= 3'd0;
    		r_data_byte[7] <= 3'd0;
    		STOP_BIT = 3'd0;
    	end
    	else if(bps_clk)begin
    		case(bps_cnt)
    			0:begin
    					START_BIT = 3'd0;
    					r_data_byte[0] <= 3'd0;
    					r_data_byte[1] <= 3'd0;
    					r_data_byte[2] <= 3'd0;
    					r_data_byte[3] <= 3'd0;
    					r_data_byte[4] <= 3'd0;
    					r_data_byte[5] <= 3'd0;
    					r_data_byte[6] <= 3'd0;
    					r_data_byte[7] <= 3'd0;
    					STOP_BIT = 3'd0;			
    				end
    			6,7,8,9,10,11:START_BIT <= START_BIT + s1_Rs232_Rx;
    			22,23,24,25,26,27:r_data_byte[0] <= r_data_byte[0] + s1_Rs232_Rx;
    			38,39,40,41,42,43:r_data_byte[1] <= r_data_byte[1] + s1_Rs232_Rx;
    			54,55,56,57,58,59:r_data_byte[2] <= r_data_byte[2] + s1_Rs232_Rx;
    			70,71,72,73,74,75:r_data_byte[3] <= r_data_byte[3] + s1_Rs232_Rx;
    			86,87,88,89,90,91:r_data_byte[4] <= r_data_byte[4] + s1_Rs232_Rx;
    			102,103,104,105,106,107:r_data_byte[5] <= r_data_byte[5] + s1_Rs232_Rx;
    			118,119,120,121,122,123:r_data_byte[6] <= r_data_byte[6] + s1_Rs232_Rx;
    			134,135,136,137,138,139:r_data_byte[7] <= r_data_byte[7] + s1_Rs232_Rx;
    			150,151,152,153,154,155:STOP_BIT <= STOP_BIT + s1_Rs232_Rx;
    			default:
    				begin
    					START_BIT = START_BIT;
    					r_data_byte[0] <= r_data_byte[0];
    					r_data_byte[1] <= r_data_byte[1];
    					r_data_byte[2] <= r_data_byte[2];
    					r_data_byte[3] <= r_data_byte[3];
    					r_data_byte[4] <= r_data_byte[4];
    					r_data_byte[5] <= r_data_byte[5];
    					r_data_byte[6] <= r_data_byte[6];
    					r_data_byte[7] <= r_data_byte[7];
    					STOP_BIT = STOP_BIT;						
    				end
    		endcase
    	end
    	
    	//7、采样数据存储模块
    	always@(posedge Clk or negedge Rst_n)
    	if(!Rst_n)
    		data_byte <= 8'd0;
    	else if(bps_cnt == 8'd159)begin
    		data_byte[0] <= r_data_byte[0][2];
    		data_byte[1] <= r_data_byte[1][2];
    		data_byte[2] <= r_data_byte[2][2];
    		data_byte[3] <= r_data_byte[3][2];
    		data_byte[4] <= r_data_byte[4][2];
    		data_byte[5] <= r_data_byte[5][2];
    		data_byte[6] <= r_data_byte[6][2];
    		data_byte[7] <= r_data_byte[7][2];
    	end	
    	
    	//8、采样状态信号处理模块
    	always@(posedge Clk or negedge Rst_n)
    	if(!Rst_n)
    		uart_state <= 1'b0;
    	else if(nedege)
    		uart_state <= 1'b1;
    	else if(Rx_Done || (bps_cnt == 8'd12 && (START_BIT > 2)))
    		uart_state <= 1'b0;
    	else
    		uart_state <= uart_state;		
    
    endmodule

模块测试脚本文件

`timescale 1ns/1ns
    `define clk_period 20
    
    module uart_byte_rx_tb;
    
    	reg Clk;
    	reg Rst_n;
    	reg Rs232_Rx;
    	
    	wire [7:0]data_byte_r;
    	wire Rx_Done;	
    	
    	reg [7:0]data_byte_t;
    	reg send_en;
    	reg [2:0]baud_set;
    	
    	wire Rs232_Tx;
    	wire Tx_Done;
    	wire uart_state;
    	
    	uart_byte_rx uart_byte_rx(
    		.Clk(Clk),
    		.Rst_n(Rst_n),
            .baud_set(baud_set),    //baud_set -->reg
    		.Rs232_Rx(Rs232_Tx),
    		
    		.data_byte(data_byte_r),
    		.Rx_Done(Rx_Done)
    	);
    	
    	uart_byte_tx uart_byte_tx(
    		.Clk(Clk),
    		.Rst_n(Rst_n),
    		.data_byte(data_byte_t),
    		.send_en(send_en),
            .baud_set(baud_set),	//baud_set --》reg
    		
            .Rs232_Tx(Rs232_Tx),   // Rs232_Tx  --》 wire
    		.Tx_Done(Tx_Done),
    		.uart_state(uart_state)
    	);
    	
        // 模块连接分析
        // uart_byte_tx.Rs232_Tx 连接到  uart_byte_rx. Rs232_Rx
        // 即让 uart_byte_tx发送，uart_byte_rx接收串口信号
    	initial Clk = 1;
    	always#(`clk_period/2)Clk = ~Clk;
    	
    	initial begin
    		Rst_n = 1'b0;			// 1、设置复位信号
    		data_byte_t = 8'd0;		// 设置数据位
    		send_en = 1'd0;			// uart_byte_tx.send_en 先暂时关闭
    		baud_set = 3'd4;		// 设置串口的发送模块和接收模块的波特率
    		#(`clk_period*20 + 1 );
    		Rst_n = 1'b1;			//2、信号复位完成
    		#(`clk_period*50);
    		data_byte_t = 8'haa;	//uart_byte_tx.data_byte_t 数据发送
    		send_en = 1'd1;		    //开启发送信号
    		#`clk_period;
    		send_en = 1'd0;          //关闭发送信号
    		
            @(posedge Tx_Done)       //检测 uart_byte_tx.Tx_Done 信号的上升沿的到来
    		
    		#(`clk_period*5000);
    		data_byte_t = 8'h55;
    		send_en = 1'd1;
    		#`clk_period;
    		send_en = 1'd0;
    		@(posedge Tx_Done)
    		#(`clk_period*5000);
    		$stop;	
    	end
    
    
    endmodule

设计uart\_rx\_top的顶层文件

module uart_rx_top(Clk,Rst_n,Rs232_Rx);
    
    	input Clk;
    	input Rst_n;
    	input Rs232_Rx;
    	
    	reg [7:0]data_rx_r;
    	wire [7:0]data_rx;
    	wire Rx_Done;
    	
    	uart_byte_rx uart_byte_rx(
    		.Clk(Clk),
    		.Rst_n(Rst_n),
    		.baud_set(3'd0),
    		.Rs232_Rx(Rs232_Rx),
    		
    		.data_byte(data_rx),
    		.Rx_Done(Rx_Done)
    	);
    	
    	issp issp(
    		.probe(data_rx_r),
    		.source()
    	);
    	
    	//该always块主要是用于issp读取数据的模块
    	always@(posedge Clk or negedge Rst_n)
    	if(!Rst_n)
    		data_rx_r <= 8'd0;
        else if(Rx_Done)   //获取到Rx_Done信号，数据data_rx_r进行更新
    		data_rx_r <= data_rx;
    	else
    		data_rx_r <= data_rx_r; //保持不变
    		
    endmodule

数据接收调试：

In-system Sources and Probes Editor 开启连续数据读取模式

![\[外链图片转存失败,源站可能有防盗链机制,建议将图片保存下来直接上传(img-vmfjyCfr-1627476172053)(E:/Blog\_Template/source/\_posts/img/blog\_img/fpga/image-20210314161235897.png)\]][img-vmfjyCfr-1627476172053_E_Blog_Template_source_posts_img_blog_img_fpga_image-20210314161235897.png]

[img-tJ10RlUP-1627476172046_img_blog_img_fpga_test.png]: /images/20220829/930b4d9bcdde49818241e96dbe8c2d6c.png
[img-nHBDRQ4S-1627476172049_img_blog_img_fpga_image-20210728204052669.png]: /images/20220829/000adb8647824219bbf86dced4c145dc.png
[img-4soaCja2-1627476172050_E_Blog_Template_source_posts_img_blog_img_fpga_image-20210312122837649.png]: /images/20220829/483bd890e7cd4cada1f71e30207d74e1.png
[img-9VThmNt8-1627476172052_E_Blog_Template_source_posts_img_blog_img_fpga_image-20210312123542400.png]: /images/20220829/f507d0c2a5524061839d2688793ad592.png
[img-vmfjyCfr-1627476172053_E_Blog_Template_source_posts_img_blog_img_fpga_image-20210314161235897.png]: /images/20220829/c68151dfb0464dd88d3408b5c0e4d6d5.png